UNIT 3

Hardware & Micro Programmed:CONTROL DESIGN Fundamental Concept , Execution of a complete instruction, Multiple-Bus organization, Hardwired Control, Micro programmed control

CONTROL DESIGN

Fundamental Concept


  • The processor fetches one instruction at a time and performs the operation specified.
  • Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered.?
  • The processor keeps track of the address of the memory location containing the next instruction to be fetched using Program Counter (PC).
  • Instruction Register (IR)

    REGISTER TRANSFERS



    All operations and data transfers are controlled by the processor clock
  • The input and output gates for register Ri are controlled by signals isRin and Riout .
  • Rin Is set to1 – data available on common bus are loaded into Ri.
  • Riout Is set to1 – the contents of register are placed on the bus.
  • Riout Is set to 0 – the bus can be used for transferring data from other registers .

    PERFORMING AN ARITHMETIC OR LOGIC OPERATION

    The ALU is a combinational circuit that has no internal storage.
  • ALU gets the two operands from MUX and bus. The result is temporarily stored in register Z.
  • What is the sequence of operations to add the contents of register R1 to those of R2 and store the result in R3?
    (a). R1out, Yin
    (b). R2out, SelectY, Add, Zin
    (c). Zout, R3in

    FETCHING A WORD FROM MEMORY

  • Address into MAR; issue Read operation; data into MDR.
  • The response time of each memory access varies (cache miss, memory-mapped I/O,…).
  • To accommodate this, the processor waits until it receives an indication that the requested operation has been completed (Memory-Function-Completed, MFC).
    • Move (R1), R2
    • MAR ? [R1]
    • Start a Read operation on the memory bus
    • Wait for the MFC response from the memory
    • Load MDR from

    It represents Timing of a memory Read operation. Assume MAR is always available on the address lines of the memory bus.

    Storing a word in memory

  • Address is loaded into MAR
  • Data to be written loaded into MDR.
  • Write command is issued.
  • Example:Move R2,(R1) R1out,MARin
    R2out,MDRin,Write
  • MDRoutE, WMFC

    Execution of a Complete Instruction

  • Add (R3), R1
  • Fetch the instruction
  • Fetch the first operand (the contents of the memory location pointed to by R3)
  • Perform the addition
  • Load the result into R1

    ARCHITECTURE OF BASIC PROCESSING UNIT

    Multiple-Bus Organization

  • Allow the contents of two different registers to be accessed simultaneously and have their contents placed on buses A and B.
  • Allow the data on bus C to be loaded into a third register during the same clock cycle.
  • Incrementer unit.
  • ALU simply passes one of its two input operands unmodified to bus C
  • control signal: R=A or R=B
  • General purpose registers are combined into a single block called registers.
  • 3 ports,2 output ports –access two different registers and have their contents on buses A and B
  • Third port allows data on bus c during same clock cycle.
  • Bus A & B are used to transfer the source operands to A & B inputs of the ALU.
  • ALU operation is performed.
  • The result is transferred to the destination over the bus C.
  • ALU may simply pass one of its 2 input operands unmodified to bus C.
  • The ALU control signals for such an operation R=A or R=B.
  • Incrementer unit is used to increment the PC by 4.
  • Using the incrementer eliminates the need to add the constant value 4 to the PC using the main ALU.
  • The source for the constant 4 at the ALU input multiplexer can be used to increment other address such as loadmultiple & storemultiple

    HARDWIRED CONTROL


    END signal is connected to a synchronous reset input of the control step counter. When END=1 in a control step, on the next rising-edge of the clock the counter resets to 0 and hence T1 becomes 1, i.e. the control unit goes to T1 to start the fetch process. Run signal is ANDED with the clock to control the step counter clock. When Run=0, the clock feeding the step counter will be 0 and the counter will not increment. When Run=1, the counter increments on the rising-edge of the clock. Run signal controls waiting until the memory finishes its operation and not go to the next control step The General Hardwired Control Unit as shown below:

    Generation of Control Signals

    For each signal, we need to find all the conditions that make it 1 by considering all the control steps that require the signal to be 1 and derive the equation for it. Let us derive the equation for the Zin signal considering only the instructions ADD R1, [R3], JMP Label, and JMPN Label for the single-bus CPU. Zin = T1 + T6 . ADD + T5 . JMP + T5 . JMPN

    Generation of Control Signals

    The equation for the END signal can be derived as: END = T7 . ADD + T6 . JMP + T4 . N’ . JMPN T6 . N . JMPN = T7 . ADD + T6 . JMP + T4 . N’ . JMPN + T6 . JMPN

    Deriving Rout & Rin Signals for Registers

    The designer needs to write execution control sequence in general such that the source and destination operands can be any register. Rout and Rin signals are derived by the control unit after the instruction is fetched and the operands are known. The general execution control sequence for the instruction ADD R0, R1 on the 1-bus CPU: T4 Rsrc,out, Yin T5 Rdst,out, ALU (C=A+B), Zin T6 Zout, Rdst,in, END

    Deriving Rout & Rin Signals for Registers

    Control unit will generate three general signals Rsrc,out, Rdst,out, and Rdst,in

    Microprogrammed Control

    In hardwired control , we saw how all the control signals required inside the CPU can be generated using a state counter and a PLA circuit. There is an alternative approach by which the control signals required inside the CPU can be generated . This alternative approach is known as microprogrammed control unit. In microprogrammed control unit , the logic of the control unit is specified by a microprogram.A microprogram consists of a sequence of instructions in a microprogramming language. These are very instructions that specify microoperations. A microprogrammed control unit is a relatively simple logic circuit that is capable of (1) sequencing through microinstructions and (2) generating control signals to execute each microinstruction. The concept of microprogram is similar to computer program. In computer program the complete instructions of the program is stored in main memory and during execution it fetches the instructions from main memory one after another. The sequence of instruction fetch is controlled by program counter (PC) . Microprogram are stored in microprogram memory and the execution is controlled by microprogram counter ( PC ) .Microprogram consists of microinstructions which are nothing but the strings of 0’s and 1’s . In a particular instance ,we read the contents of one location of microprogram memory , which is nothing but a microinstruction . Each output line ( data line ) of microprogram memory corresponds to one control signal. If the contents of the memory cell is ) , it indicates that the signal is to generated and if the contents of memory cell is 1 , it indicates that generate that control signal at that instant of time. First let me define the different terminologies that are related to microprogrammed control unit.

    Control Word (CW)

    Control word is defined as a word whose individual bits represent the various control signal. Therefore each of the control steps in the control sequence of an instruction defines a unique combination of 0s and 1s in the CW. A sequence of control words ( CWs ) corresponding to the control sequence of a machine instruction constitutes the microprogram for that instruction. The designer needs to write execution control sequence in general such that the source and destination operands can be any register. Rout and Rin signals are derived by the control unit after the instruction is fetched and the operands are known. The general execution control sequence for the instruction ADD R0, R1 on the 1-bus CPU: T4 Rsrc,out, Yin T5 Rdst,out, ALU (C=A+B), Zin T6 Zout, Rdst,in, END

    Deriving Rout & Rin Signals for Registers

    Control unit will generate three general signals Rsrc,out, Rdst,out, and Rdst,in The individual control words in this microprogram are referred to as microinstructions. The microprograms corresponding to the instruction set of a computer are stored ina aspecial memory which will be referred to as the microprogram memory. The control words related to an instructions are stored in microprogram memory. The control unit can generate the control signals for any instruction by sequencially reading the CWs of the corresponding microprogram from the microprogram memory. To read the control word sequentially from the microprogram memory a microprogram counter ( PC ) is needed. The basic organization of a microprogrammed control unit is shown in the figure. The “starting address generator “ block is responsible for loading the starting address of the microprogram into the PC everytime a new instruction is loaded in the IR. The PC is then automatically incremented the clock, and it reads the successive microinstruction from memory . Each microinstruction basically provides the required control signal at that time step. The microprogram counter ensures that the control signal will be delivered to the various parts of the CPU in correct sequence. We have some instructions whose execution depends on the status of condition codes and status flag , as for example , the branch instruction. During branch instruction execution it is required to take the decision between the alternative action. To handle such type of instructions with microprogrammed control , the design of control unit is based on the concept of conditional branching in the microprogram. For that it is required to include some conditional branch microinstructions. In conditional microinstructions , it is required to specify the address of the microprogram memory to which the control must direct. It is known as branch address. Apart from branch address , these microinstructions can specify which of the states flags , condition codes , or possibly , bits of the instruction register should be checked as a condition for branching to take place. To support microprogram branching , the organization of control unit should be odified to accommodate the branching decision. To generate the branch address , it is required to know the status of the condition codes and status flag . To generate the starting address , we need the instruction which is present in IR. But for branch address generation we have to check the content of condition codes and status flag. The organization of control unit to enable conditional branching in the microprogram is shown in the figure.

    The control bits of the microinstructions word which specify the branch conditions and address are fed to the “ Starting and branch address generator “ block. This block performs the function of loading a new address into the PC when the condition of branch instruction is satisfied. In a computer program we have seen that execution of every instruction consists of two part – fetch phase and execution phase of the instruction. It is also observed that the fetch phase of all instruction is same. In microprogrammed controlled control unit , a common microprogram is used to fetch the instruction. This microprogram is stored in a specific location and execution of each instruction start from that memory location. At the end of fetch microprogram , the starting address generator unit calculate the appropriate starting address of the microprogram for the instruction which is currently present in IR. After the PC controls the execution of microprogram which generates the appropriate control signal in proper sequence. During the execution of a microprogram , the PC is always incremented everytime a new microinstruction is fetched from the microprogram memory , except in the following situations :
    1. When an End instruction is encountered , the PC is loaded with the address of the first CW in the microprogram for the instruction fetch cycle.
    2. When a new instruction is loaded into the IR , the PC is loaded with the starting address of the microprogram for that instruction.
    3. When a branch microinstruction is encountered , and the branch condition is satisfied , the PC is loaded with the branch address.

    Microprogram Sequencing

    1. If all microprograms require only straightforward sequential execution of microinstructions except for branches, letting a µPC governs the sequencing would be efficient.
    2. However, two disadvantages:
      • Having a separate microroutine for each machine instruction results in a large total number of microinstructions and a large control store.
      • Longer execution time because it takes more time to carry out the required branches. Example: Add src, Rdst,/li>
    3. Four addressing modes: register, autoincrement, autodecrement, and indexed (with indirect forms)
    4. .

    Microinstructions with Next-Address Field

    • The microprogram we discussed requires several branch microinstructions, which perform no useful operation in the datapath.
    • A powerful alternative approach is to include an address field as a part of every microinstruction to indicate the location of the next microinstruction to be fetched.
    • Pros: separate branch microinstructions are virtually eliminated; few limitations in assigning addresses to microinstructions.
    • Cons: additional bits for the address field (around 1/6)